LVDCI - LVDCI - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English
Table 1. Available I/O Bank Type
HD HP XP5IO
N/A Available Available

Using these I/O buffers configures the outputs as controlled impedance drivers. The receiver of low-voltage digitally controlled impedance (LVDCI) is identical to an LVCMOS receiver. Some I/O standards, such as LVCMOS, must have a drive impedance that matches the characteristic impedance of the driven line. The HP I/O banks provide a controlled impedance output driver to provide series termination without external-source termination resistors.

Source termination is controlled using the OUTPUT_IMPEDANCE attribute. The only valid value of this attribute for LVDCI standards is RDRV_48_48, which corresponds to a 48 Ω setting.

Sample circuits illustrating both unidirectional and bidirectional topologies for a controlled impedance driver are shown in the following figures. The DCI I/O standards supporting a controlled impedance driver are: LVDCI_15 and LVDCI_18 (HP I/O banks only).

Figure 1. Unidirectional Controlled Impedance Driver Topology
Figure 2. Bidirectional Controlled Impedance Driver Topology

The following table details the allowed attributes that can be applied to the LVDCI I/O standard. This standard is available in the HP I/O banks. Support is implied for primitives that are derivatives of the primitives listed in the following table (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to SelectIO IOB Interface Primitives for all supported derivatives.

Table 2. Allowed Attributes for the LVDCI I/O Standards
Attributes Primitives
IBUF OBUF/OBUFT/IOBUF
Allowed Values Default
IOSTANDARD LVDCI_15, LVDCI_18 (HP I/O banks only) LVDCI_15, LVDCI_18 (HP I/O banks only)
SLEW N/A FAST, MEDIUM, SLOW SLOW
OUTPUT_IMPEDANCE N/A RDRV_48_48