As device footprints increase and system clock speeds get faster, PC board design and manufacturing becomes more difficult. With ever faster edge rates, maintaining signal integrity becomes a critical issue. PC board traces must be properly terminated to avoid reflections or ringing.
To terminate a trace, resistors are traditionally added to make the output and/or input match the impedance of the receiver or driver to the impedance of the trace. However, due to increased device I/O density, adding resistors close to the device pins increases the board area and component count, and can in some cases be physically impossible. To address these issues and to achieve better signal integrity, AMD developed the digitally controlled impedance (DCI) technology.
Depending on the I/O standard, DCI can either control the output impedance of a driver, or add a parallel termination present at the receiver, with the goal of accurately matching the characteristic impedance of the transmission line. DCI calibrates the termination structures inside the I/O to calibrate to an external precision reference resistor placed on the VRP (HP) or VR (XP5IO) pin. This compensates for changes in I/O impedance due to process variation. HP banks can continuously adjust the impedance to compensate for variations of temperature and supply voltage fluctuations. Each HP bank that uses DCI requires a DCI reference VRP pin is connected to ground through a 240 Ω resistor. There is only one VR pin that is shared across all XP5IO banks in a device that must be tied to VCCO through a 240 Ω resistor.
For the I/O standards with controlled parallel termination, DCI provides the parallel termination for receivers. This eliminates the need for termination resistors on the board, reduces board routing difficulties and component count, and improves signal integrity by eliminating stub reflection. Stub reflection occurs when termination resistors are located too far from the end of the transmission line. With DCI, the termination resistors are as close as possible to the output driver or the input buffer, thus eliminating stub reflections. The exact value of the termination resistors is determined by the ODT attribute for controlled parallel termination. The exact driver termination value is determined by the OUTPUT_IMPEDANCE attribute for the controlled impedance driver. DCI is not available in HD I/O banks.
DCI in HP I/O Banks
For DCI in HP I/O banks, there is one multi-purpose reference VRP pin in each HP I/O bank to control the impedance of the driver or the parallel-termination value for all of the I/Os of that bank.
To implement DCI in an HP I/O:
- Assign one of the DCI I/O standards in an HP I/O bank (see Table 1).
- Connect the VRP multi-function pin to a precision resistor (240 Ω) tied to GND.
- Set the desired termination value using the ODT attribute for all applicable I/Os with controlled parallel terminations. Set the termination value using the OUTPUT_IMPEDANCE attribute for all applicable I/Os with a controlled impedance driver.
With DCI cascading, one I/O bank (the master bank) must have its VRN/VRP pins connected to external reference resistors. Other I/O banks in the same HP I/O bank column (slave banks) can use DCI standards with the same impedance as the master bank, without connecting the VRN/VRP pins on these slave banks to external resistors. DCI impedance control in cascaded banks is received from the I/O master bank.
set_property DCI_CASCADE {slave_bank_number} [get_iobanks master_bank_number]DCI cascading is only available through a column of HP I/O banks that adhere to the following restrictions:
- The master and slave SelectIObanks must all reside on the same HP I/O column on the device
- Master and slave I/O banks must have the same VCCO and VREF (if applicable) voltage.
- I/O banks in the same HP I/O column that are not using DCI (pass-through banks) do not have to comply with the VCCO and VREF voltage rules for combining DCI settings.
- DCI I/O banking compatibility rules must be satisfied across all master and slave banks (for example, only one DCI I/O standard using single termination type is allowed across all master and slave banks).
DCI in XP5IO Banks
The VR pin is used to calibrate on-die termination to a reference resistor on the PCB. For example, bank 86 has a VR pin in bank 86 called VR_86. VR pins must be externally connected to a 240 Ω resistor on the PCB and pulled up to the bank VCCO voltage. Unlike HP I/O banks, all IOSTANDARDs in an XP5IO bank that support ODT or OUTPUT_IMPEDANCE enable termination.
DCI adjusts the impedance of the I/O by selectively turning resistors in the I/Os on or off. The adjustment starts during the device start-up sequence. By default, the DONE pin does not transition High until the first part of the impedance adjustment process is completed.
In HP I/O, DCI calibration can be reset by instantiating the DCIRESET primitive. Toggling the RST input to the DCIRESET primitive while the device is operating resets the DCI state machine and restarts the calibration process. All HP I/Os using DCI are unavailable until the LOCKED output from the DCIRESET block is asserted. This functionality is useful in applications where the temperature and/or supply voltage changes significantly from device power-up to the nominal operating condition.
For controlled impedance output drivers, the exact value of the driver terminations is determined by the OUTPUT_IMPEDANCE attribute. For the I/O standards that support parallel termination, DCI creates a Thevenin equivalent or split-termination resistance to the VCCO/2 voltage level, or a single-termination resistance to the VCCO voltage level. The value of split-termination resistors are determined by the ODT attribute. For POD and HSUL standards, DCI supports single termination to VCCO. For LVSTL (XP5IO I/O only), DCI supports single termination to GND. The value of the termination resistance is determined by the ODT attribute.