Internal VREF in HP I/O Banks - Internal VREF in HP I/O Banks - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

An optional VREF scan feature in HP I/O banks helps to fine tune the internal VREF of input buffers to maximize the performance for a subset of I/O standards. This feature can be accessed through the IBUFE3 and IOBUFE3 primitives with the HPIO_VREF primitive as shown in the following figure. VREF scan requires building control logic into your interconnect logic design.

Figure 1. Connection from the Interconnect Logic to Access the VREF Scan Feature

Internal VREF in HP I/O Banks

Internal VREF tuned using the VREF scan feature controls the VREF of 13 consecutive I/Os (1 byte group) within a bank as shown in the following figure. There are four byte groups within a bank. Four different variations of a given VREF are possible within a bank (for four byte groups in each bank). However, to use this feature, the central VREF of the bank needs to be set using the INTERNAL_VREF attribute (See Internal VREF). Inputs with I/O standards of different VREF specifications cannot be placed within the same bank. Tuned VREF connection (VREF output of HPIO_VREF primitive) cannot traverse byte group boundaries.

Figure 2. VREF Scan Connection per Byte Group within a Bank

Internal VREF (INTERNAL_VREF and VREF scan) cannot be combined with external VREF usage within a bank. VREF_CNTR is used with the HPIO_VREF UNISIM primitive to set the VREF scan-range based on the I/O standard.

The valid values for the VREF_CNTR attribute are described here:

  • FABRIC_RANGE1 (POD standards)
  • FABRIC_RANGE2 (other applicable standards)

FABRIC_RANGE1 is used with the POD standards and the FABRIC_RANGE2 is used with the other applicable standards when the receiver VREF scan feature is invoked. The FABRIC_VREF_TUNE[6:0] port is used to tune the VREF from the interconnect logic. The approximate value of VREF for various values in reference to FABRIC_VREF_TUNE and VREF_CNTR is shown in the following table.

Table 1. Approximate VREF Value as a Result of Using the VREF Scan Function
FABRIC_TUNE_VREF[6:0] VREF (% of VCCO)
VREF_CNTR = FABRIC_RANGE1 VREF_CNTR = FABRIC_RANGE2
000 0001 58.00% 43.00%
000 0010 58.50% 43.50%
000 0011 59.00% 44.00%
000 0100 59.50% 44.50%
000 0101 60.00% 45.00%
000 0110 60.50% 45.50%
000 0111 61.00% 46.00%
000 1000 61.50% 46.50%
000 1001 62.00% 47.00%
000 1010 62.50% 47.50%
000 1011 63.00% 48.00%
000 1100 63.50% 48.50%
000 1101 64.00% 49.00%
000 1110 64.50% 49.50%
000 0000 65.00% 50.00%
000 1111 65.50% 50.50%
001 0000 66.00% 51.00%
001 0001 66.50% 51.50%
001 0010 67.00% 52.00%
001 0011 67.50% 52.50%
001 0100 68.00% 53.00%
001 0101 68.50% 53.50%
001 0110 69.00% 54.00%
001 0111 69.50% 54.50%
001 1000 70.00% 55.00%
001 1001 70.50% 55.50%
001 1010 71.00% 56.00%
001 1011 71.50% 56.50%
001 1100 72.00% 57.00%
001 1101 72.50% 57.50%
001 1110 73.00% 58.00%
001 1111 73.50% 58.50%
010 0000 74.00% 59.00%
010 0001 74.50% 59.50%
010 0010 75.00% 60.00%
010 0011 75.50% 60.50%
010 0100 76.00% 61.00%
010 0101 76.50% 61.50%
010 0110 77.00% 62.00%
010 0111 77.50% 62.50%
010 1000 78.00% 63.00%
010 1001 78.50% 63.50%
010 1010 79.00% 64.00%
010 1011 79.50% 64.50%
010 1100 80.00% 65.00%
010 1101 80.50% 65.50%
010 1110 81.00% 66.00%
010 1111 81.50% 66.50%
011 0000 82.00% 67.00%
011 0001 82.50% 67.50%
011 0010 83.00% 68.00%
011 0011 83.50% 68.50%
011 0100 84.00% 69.00%
011 0101 84.50% 69.50%
011 0110 85.00% 70.00%
011 0111 85.50% 70.50%
011 1000 86.00% 71.00%
011 1001 86.50% 71.50%
011 1010 87.00% 72.00%
011 1011 87.50% 72.50%
011 1100 88.00% 73.00%
011 1101 88.50% 73.50%
011 1110 89.00% 74.00%
011 1111 89.50% 74.50%
100 0000 90.00% 75.00%
100 0001 90.50% 75.50%
100 0010 91.00% 76.00%
100 0011 91.50% 76.50%
100 0100 92.00% 77.00%
100 0101 92.50% 77.50%
100 0110 93.00% 78.00%
100 0111 93.50% 78.50%
100 1000 94.00% 79.00%

Internal VREF in XP5IO I/O Banks

Internal VREF tuning using the XP5IO_VREF primitive controls the VREF of six consecutive I/Os (one nibble group) within a bank as shown in the following figure. Inputs with I/O standards of different VREF specifications cannot be placed within the same bank. A tuned VREF connection (VREF output of the XP5IO_VREF primitive) cannot traverse nibble boundaries.

Figure 3. VREF Scan Connection per Nibble within a Bank

The 10-bit FABRIC_VREF_TUNE value provides scaling factors as a percentage of VCCO as follows:

FABRIC_VREF_TUNE[9:0] = % VCCO × 1024 for LVSTL05_10, LVSTL_11, and LVSTL06_12

For example, LVSTL06_12 uses the first equation and has a nominal VREF level of 150 mV (or 12.5% of VCCO). Because LVSTL06_12 is powered with a VCCO of 1.2V, a FABRIC_VREF_TUNE value of 0010000000 or 128 can be used, as 128 (or 0010000000 = 0.125 × 1024 = 12.5% × 1.2V = 150 mV.

FABRIC_VREF_TUNE[9:0] = % VCCO × 512 for all other IOSTANDARDS

For example, SSTL12 has a target VREF level of approximately 600 mV (50% VCCO). A FABRIC_VREF_TUNE value of 0100000000 or 256 = 0.5 × 512 = 50% × 1.2V = 600 mV.

Important: Input signals for all standards other than LVSTL_11, LVSTL06_12, and LVSTL05_10 are scaled by 50% compared to VREF. The VREF scan value must be chosen to account for the scaled value. For example, because SSTL12's target VREF is 50% VCCO, the VREF scan value should be 0100000000, or 25% VCCO, because the input signal is scaled before reaching the receiver. The Vivado tools always report VREF levels relative to the input pin level (unscaled).

To set custom receiver VREF levels, the XP5IO_VREF primitive can be used to assign a specific voltage level using the FABRIC_VREF_TUNE port as illustrated in the HPIO_VREF example above, but with a 10-bit FABRIC_VREF_TUNE port. An optional VREF scan feature in XP5IO I/O banks helps to fine tune the internal VREF of input buffers to maximize the performance for a subset of I/O standards.

The XP5IO_VREF primitive is autoplaced to the appropriate XP5IO_VREF site, and the VREF_NIB must be set to VREF_FABRIC. The following XDC command can be used:

set_property VREF_NIB VREF_FABRIC [get_cells XP5IO_VREF_inst]