IDDRE1 Attributes - IDDRE1 Attributes - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The following table lists the IDDRE1 attributes.

Table 1. IDDRE1 Attributes
Attribute Values Default Type Description
DDR_CLK_EDGE

OPPOSITE_EDGE

SAME_EDGE

SAME_EDGE_PIPELINED

OPPOSITE_EDGE String Sets the IDDRE1 mode of operation with respect to clock edge.
IS_C_INVERTED 0 or 1 0 Bit Sets a local clock inversion for C input when 1.
IS_CB_INVERTED 0 or 1 0 Bit Sets a local clock inversion for CB input. When IS_CB_INVERTED = 1, C and CB must be driven by the same global clock buffer. When IS_CB_INVERTED = 0, CB must be driven by the same global clock buffer through an inverter.