I/O Tile Overview - I/O Tile Overview - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The AMD Spartan™ UltraScale+™ devices provide high-performance (HP), high-density (HD), and XP5IO offerings. Although HP I/O and HD I/O resources are similar to other UltraScale+ device resources, the Spartan UltraScale+ family has subtle differences. These differences, along with the unique XP5IO warrant this unique SelectIO™ user guide specific to the Spartan UltraScale+ family .

Note: For all other UltraScale+ families, refer to UltraScale Architecture SelectIO Resources User Guide (UG571).
  • The HP I/O banks are designed to meet the performance requirements of high-speed memory and other chip-to-chip interfaces with voltages between 1.0V and 1.8V.
  • The HD I/O banks are designed to support low-speed interfaces with voltages between 1.2V and 3.3V.
  • The XP5IO banks are designed to enhance I/O support for LPDDR5 interfaces as well as improving performance on high-speed interfaces like MIPI D-PHY. XP5IO are powered with a voltage between 1.0V and 1.5V but can be used to interface with lower voltage LVSTL interfaces.

Spartan UltraScale+ devices contain different combinations of HP, HD, and XP5IO I/O banks, though not all types of banks or pins within a bank are supported in all devices. The UltraScale Architecture and Product Data Sheet: Overview (DS890) documents the available number of each type of bank for all devices.

The Spartan UltraScale+ family has high-performance I/O banks (HP and XP5IO) with MIPI D-PHY capabilities and the corresponding logic resources. They also have high-density I/Os (HD I/Os) with corresponding logic resources.

The following table highlights the features supported in the HP, HD, and XP5IO banks. See Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) for details on the performance and other electrical requirements of the HP, HD, and XP5IO banks.

Table 1. Supported Features in the HD, HP, and XP5IO Banks
Feature HP I/O Banks HD I/O Banks XP5IO Banks
3.3V I/O standards 1 N/A Supported N/A
2.5V I/O standards 1 N/A Supported N/A
1.8V I/O standards 1 Supported Supported N/A
1.5V I/O standards 1 Supported Supported Supported
1.35V I/O standards 1 Supported Supported Supported
1.2V I/O standards 1 Supported Supported Supported
1.0V I/O standards 1 Supported Not supported Supported
LVDS signaling 2 Supported at 1.8V Supported (input only) Supported at 1.5V
Digitally-controlled impedance (DCI) Supported Not supported Supported
Internal VREF Supported Supported Supported
Internal differential termination (DIFF_TERM) Supported Not supported Supported
Input delay Supported Not supported Supported
Output delay Supported Not supported Supported
Dedicated serialization resource Supported (8:1, 4:1) Not supported Supported (8:1, 4:1, 2:1)
Dedicated deserialization resources Supported (1:8, 1:4) Not supported Supported (1:8, 1:4, 1:2)
Transmitter pre-emphasis Supported Not supported Supported
Receiver equalization Supported Not supported Supported
Receiver offset control Supported Not supported Not Supported
Receiver VREF scan Supported Not supported Supported
MIPI D-PHY Supported Not supported Supported
LPDDR5 compatibility Not supported Not supported Supported
  1. Supported I/O Standards and Terminations shows the specific I/O standards that are available by bank type.
  2. Although LVDS is generally considered a 2.5V I/O standard, it is supported at 1.8V in HP I/O banks and 1.5V in XP5IO banks. Compatibility should be verified in the UltraScale device data sheets.