High Speed Unterminated Logic (HSUL_12) - High Speed Unterminated Logic (HSUL_12) - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The HSUL_12 standard is for LPDDR2 and LPDDR3 memory buses. HSUL_12 is defined by the JEDEC standard JESD8-22. Spartan UltraScale+ devices support this standard for single-ended signaling and differential signaling. Similar to SSTL, this standard also requires a differential amplifier input buffer and a push-pull output buffer.