HSTL_I_12 - HSTL_I_12 - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English
Table 1. Available I/O Bank Type
HD HP XP5IO
N/A Available Available

HSTL_I_12 uses VCCO/2 as a parallel-termination voltage (VTT). Optional untuned split input ODT provides Thevenin equivalent resistance of R (where R = Z0) to the VCCO/2 in HP I/O banks. The untuned on-die source termination feature (OUTPUT_IMPEDANCE) with optional 40 Ω, 48 Ω, or 60 Ω of driver impedance is available in HP I/O banks. In XP5IO I/O banks, termination is always calibrated. The default value of the driver output impedance is 48 Ω.