HSTL_I and HSTL_ I_18 - HSTL_I and HSTL_ I_18

HSTL_I and HSTL_ I_18 - HSTL_I and HSTL_ I_18 - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID

UG861

Release Date

2026-04-28

Revision

1.1 English

Table 1. HSTL_I Available I/O Bank Type
HD	HP	XP5IO
Available	Available	Available

Table 2. HSTL_I_18 Available I/O Bank Type
HD	HP	XP5IO
Available	Available	N/A

HSTL_I and HSTL_ I_18 use V_CCO/2 as a parallel-termination voltage (V_TT). Optional untuned split input ODT provides Thevenin equivalent resistance of R (where R = Z₀) to the V_CCO/2. The untuned on-die source termination feature (OUTPUT_IMPEDANCE) with optional 40 Ω, 48 Ω, or 60 Ω of driver impedance is available in HP I/O banks only. In XP5IO I/O banks, termination is always calibrated. The default value of the driver output impedance is 48 Ω.