HSTL_ I_DCI, HSTL_I_DCI_12, and HSTL_ I_DCI_18 - HSTL_ I_DCI, HSTL_I_DCI_12, and HSTL_ I_DCI_18

HSTL_ I_DCI, HSTL_I_DCI_12, and HSTL_ I_DCI_18 - HSTL_ I_DCI, HSTL_I_DCI_12, and HSTL_ I_DCI_18 - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID

UG861

Release Date

2026-04-28

Revision

1.1 English

Table 1. Available I/O Bank Type
HD	HP	XP5IO
N/A	Available	N/A

In Spartan UltraScale+ devices, HSTL_I_DCI and HSTL_I_DCI_18 provide on-chip split-Thevenin termination powered from V_CCO, using the ODT attribute, creating an equivalent parallel-termination voltage (V_TT) of V_CCO/2. HSTL_I_DCI_12 does not provide input split termination in Spartan UltraScale+ devices. SSTL12_DCI provides equivalent functionality.

The source termination feature (OUTPUT_IMPEDANCE) provides the option of 40 Ω, 48 Ω, or 60 Ω of tuned driver impedance in HP I/O banks. The default value of the driver output impedance is 48 Ω.