HSTL Allowed Attributes - HSTL Allowed Attributes

HSTL Allowed Attributes - HSTL Allowed Attributes - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID

UG861

Release Date

2026-04-28

Revision

1.1 English

The following tables list the supported attributes for the HSTL I/O standards. Support is implied for primitives that are derivatives of the primitives listed in these tables (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to SelectIO IOB Interface Primitives for all supported derivatives.

Table 1. HSTL Class I Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	HSTL_I HSTL_I_12 HSTL_I_18 (HP I/O banks only)		HSTL_I HSTL_I_18		HSTL_I HSTL_I_12 HSTL_I_18 (HP I/O banks only)		HSTL_I HSTL_I_18		HSTL_I HSTL_I_12 HSTL_I_18 (HP I/O banks only)		HSTL_I HSTL_I_18
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW	FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW
ODT	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	N/A	N/A	N/A		N/A		RTT_40 RTT_48 RTT_60 RTT_NONE¹	RTT_NONE	RTT_48 RTT_NONE	RTT_NONE
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60¹	RDRV_48_48	N/A
The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table 5.

Table 2. HSTL Class I DCI Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP I/O		HD and XP5IO I/O		HP I/O		HD and XP5IO I/O		HP I/O		HD and XP5IO I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	HSTL_I_DCI HSTL_I_DCI_12 HSTL_I_DCI_18		N/A		HSTL_I_DCI HSTL_I_DCI_12 HSTL_I_DCI_18		N/A		HSTL_I_DCI HSTL_I_DCI_12 HSTL_I_DCI_18		N/A
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	N/A		FAST MEDIUM SLOW	SLOW	N/A
ODT	RTT_40 RTT_48 RTT_60²	RTT_48	N/A		N/A		N/A		RTT_40 RTT_48 RTT_60^{1, 2}	RTT_48	N/A
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60¹	RDRV_48_48	N/A
The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table 5. ODT = RTT_NONE is not a valid setting for DCI I/O standards.

Table 3. DIFF_HSTL Class I Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	DIFF_HSTL_I DIFF_HSTL_I_12 DIFF_HSTL_I_18 (HP I/O only)		DIFF_HSTL_I DIFF_HSTL_I_18		DIFF_HSTL_I DIFF_HSTL_I_12 DIFF_HSTL_I_18 (HP I/O only)		DIFF_HSTL_I DIFF_HSTL_I_18		DIFF_HSTL_I DIFF_HSTL_I_12 DIFF_HSTL_I_18 (HP I/O only)		DIFF_HSTL_I DIFF_HSTL_I_18
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW	FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW
ODT	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	RTT_48 RTT_NONE	RTT_NONE	N/A		N/A		RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	RTT_48 RTT_NONE	RTT_NONE
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A
The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table 5.

Table 4. DIFF_HSTL Class I DCI Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP I/O		HD and XP5IO I/O		HP I/O		HD and XP5IO I/O		HP I/O		HD and XP5IO I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_12 DIFF_HSTL_I_DCI_18		N/A		DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_12 DIFF_HSTL_I_DCI_18		N/A		DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_12 DIFF_HSTL_I_DCI_18		N/A
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	N/A		FAST MEDIUM SLOW	SLOW	N/A
ODT	RTT_40 RTT_48 RTT_60²	RTT_48	N/A		N/A		N/A		RTT_40 RTT_48 RTT_60^{1, 2}	RTT_48	N/A
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60¹	RDRV_48_48	N/A
The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table 5. ODT = RTT_NONE is not a valid setting for DCI I/O standards.

Table 5. Only Allowed Combinations for Bidirectional Configurations in HP I/O Banks
OUTPUT_IMPEDANCE	ODT
RDRV_40_40 (40 Ω)	RTT_40
RDRV_40_40 (40 Ω)	RTT_60
RDRV_40_40 (40 Ω)	RTT_NONE
RDRV_48_48 (48 Ω)	RTT_48
RDRV_48_48 (48 Ω)	RTT_NONE
RDRV_60_60 (60 Ω)	RTT_40
RDRV_60_60 (60 Ω)	RTT_60
RDRV_60_60 (60 Ω)	RTT_NONE