HSLVDCI - HSLVDCI - UG861

The driver is identical to LVDCI, while the input is identical to HSTL and SSTL. By using a V_REF -referenced input, high-speed LVDCI (HSLVDCI) allows greater input sensitivity at the receiver than when using a single-ended LVCMOS-type receiver.

The HP and XP5IO I/O banks have a controlled impedance output driver to provide series termination without external-source termination resistors. The only valid value of the OUTPUT_IMPEDANCE attribute for HSLVDCI standards is RDRV_48_48, which corresponds to a 48 Ω setting.

A sample circuit illustrating bidirectional termination techniques for an HSLVDCI controlled impedance driver is shown in the following figure. The DCI I/O standards supporting a controlled impedance driver with a V_REF referenced input are: HSLVDCI_15 and HSLVDCI_18 (HP I/O banks only).

For electrical specifications, see the LVDCI V_OH and V_OL entries in the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) .

The following table details the allowed attributes that can be applied to the HSLVDCI I/O standard. This standard is available in the HP I/O banks. Support is implied for primitives that are derivatives of the primitives listed in the following table (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to SelectIO IOB Interface Primitives for all supported derivatives.