High-density (HD) I/O banks are SelectIO resources designed to support a wide range of I/O standards with voltages ranging from 1.2V to 3.3V. HD I/Os are optimized for single-ended, voltage-referenced, and pseudo-differential I/O standards operating at lower data rates. Limited support for true differential inputs (with external termination) is also available to support LVDS and LVPECL clock inputs. HD I/Os also contain interface logic including registers and static delay lines to support asynchronous, system synchronous, and clock-based source synchronous interfaces. SelectIO IOB Technology and Supported Standards highlights the features supported in HD I/O banks.
HD I/O pins contain an I/O interface (IOI) logic block that enables various I/O interfaces. HD I/O IOI consists of an OLOGIC and ILOGIC block dedicated for each pin.
Supported interfaces include the following:
- Asynchronous (or combinatorial) input and output interfaces
- System synchronous interfaces
with SDR registers in the IOI and/or interconnect logic. Supported
flip-flop primitives include the following:
- FDCE: Flip-flop with clock enable and asynchronous clear
- FDPE: Flip-flop with clock enable and asynchronous preset
- FDRE: Flip-flop with clock enable and synchronous reset
- FDSE: Flip-flop with clock enable and synchronous set
- Source synchronous interfaces with DDR registers in the IOI and/or interconnect logic. Supported primitives include IDDRE1 and ODDRE1.
Performance Considerations
The HDIO performance specifications are design dependent. Although the logic resources can operate at specified switching frequencies, design resources can heavily influence clock to data phase alignment and actual performance. Due to a lack of dedicated phase alignment circuitry, and the fact that the registering clock must traverse the global clock network, IOSTANDARD select, clock network delay, and clock to data uncertainty can all reduce HD interface logic performance.