Differential SSTL18, SSTL15, SSTL135, SSTL12 Termination - Differential SSTL18, SSTL15, SSTL135, SSTL12 Termination

Differential SSTL18, SSTL15, SSTL135, SSTL12 Termination - Differential SSTL18, SSTL15, SSTL135, SSTL12 Termination - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document_ID

UG861

Release_Date

2026-04-28

Revision

1.1 English

The following figure shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with unidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (that is, DIFF_SSTL12 should only interface with DIFF_SSTL12).

Note: HD I/Os only support DIFF_SSTL12 in receive mode. Output and bidirectional buffers do not support DIFF_SSTL12 in HD I/O banks.

Figure 1. Differential SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional Termination

The following figure shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with unidirectional DCI termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (that is, DIFF_SSTL12_DCI should only interface with DIFF_SSTL12_DCI).

Figure 2. Differential SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional DCI Termination

The following figure shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with bidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (that is, DIFF_SSTL12 should only interface with DIFF_SSTL12).

Figure 3. Differential SSTL18, SSTL15, SSTL135, or SSTL12 with Bidirectional Termination

The following figure shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with bidirectional DCI termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (that is, DIFF_SSTL12_DCI should only interface with DIFF_SSTL12_DCI). DCI standards are supported only in HP I/Os.

Figure 4. Differential SSTL18, SSTL15, SSTL135, or SSTL12 with Bidirectional DCI Termination

The following table lists the allowed attributes for SSTL I/O standards. Support is implied for primitives that are derivatives of the primitives listed in the following table (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to SelectIO IOB Interface Primitives for all supported derivatives.

Table 1. Single-Ended SSTL Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	SSTL12 SSTL135 SSTL15 SSTL18_I (HP only)		SSTL12 SSTL135 SSTL15 SSTL18_I SSTL135_II SSTL18_II SSTL15_II		SSTL12 SSTL135 SSTL15 SSTL18_I (HP only)		SSTL135 SSTL15 SSTL18_I		SSTL12 SSTL135 SSTL15 SSTL18_I (HP only)		SSTL135 SSTL15 SSTL18_I
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW	FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW
ODT	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	RTT_48 RTT_NONE	RTT_NONE	N/A		N/A		RTT_40 RTT_48 RTT_60 RTT_NONE¹	RTT_NONE	RTT_48 RTT_NONE	RTT_NONE
OUTPUT_IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_40_40	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60¹	RDRV_40_40	N/A
The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table 5.

Table 2. Single-Ended SSTL DCI Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP I/O		HD and XP5IO I/O		HP I/O		HD and XP5IO I/O		HP I/O		HD and XP5IO I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	SSTL12_DCI SSTL135_DCI SSTL15_DCI SSTL18_I_DCI		N/A		SSTL12_DCI SSTL135_DCI SSTL15_DCI SSTL18_I_DCI		N/A		SSTL12_DCI SSTL135_DCI SSTL15_DCI SSTL18_I_DCI		N/A
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	N/A		FAST MEDIUM SLOW	SLOW	N/A
ODT	RTT_40 RTT_48 RTT_60	RTT_40	N/A		N/A		N/A		RTT_40 RTT_48 RTT_60^{1, 2}	RTT_40	N/A
OUTPUT_IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_40_40	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60¹	RDRV_40_40	N/A
The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table 5. ODT = RTT_NONE is not a valid setting for DCI I/O standards.

Table 3. DIFF_SSTL Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I (HP I/O only)		DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I DIFF_SSTL135_II DIFF_SSTL18_II DIFF_SSTL15_II		DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I (HP I/O only)		DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I		DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I (HP I/O only)		DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW	FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW
DQS_BIAS¹	TRUE FALSE	FALSE	N/A	N/A	N/A		N/A		TRUE FALSE	FALSE	TRUE FALSE	FALSE
ODT	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	RTT_48 RTT_NONE	RTT_NONE	N/A		N/A		RTT_40 RTT_48 RTT_60 RTT_NONE²	RTT_NONE	RTT_48 RTT_NONE	RTT_NONE
OUTPUT_IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_40_40	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60²	RDRV_40_40	N/A
The DQS_BIAS attribute is set on the I/O port rather than the primitive. The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table 5.

Table 4. DIFF_SSTL DCI Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP I/O		HD and XP5IO I/O		HP I/O		HD I/O		HP and XP5IO I/O		HD I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	DIFF_SSTL12_DCI DIFF_SSTL135_DCI DIFF_SSTL15_DCI DIFF_SSTL18_I_DCI		N/A		DIFF_SSTL12_DCI DIFF_SSTL135_DCI DIFF_SSTL15_DCI DIFF_SSTL18_I_DCI		N/A		DIFF_SSTL12_DCI DIFF_SSTL135_DCI DIFF_SSTL15_DCI DIFF_SSTL18_I_DCI		N/A
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	N/A		FAST MEDIUM SLOW	SLOW	N/A
DQS_BIAS^{1, 2}	TRUE FALSE	FALSE	N/A		N/A		N/A		TRUE FALSE	FALSE	N/A
ODT	RTT_40 RTT_48 RTT_60³	RTT_40	N/A		N/A		N/A		RTT_40 RTT_48 RTT_60^{3, 4}	RTT_40	N/A
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_40_40	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60¹	RDRV_40_40	N/A
The DQS_BIAS attribute is set on the I/O port rather than the primitive. This is read-only on the primitive. ODT = RTT_NONE is not a valid setting for DCI I/O standards. The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table 5.