Differential HSUL_12 Termination - Differential HSUL_12 Termination

Differential HSUL_12 Termination - Differential HSUL_12 Termination - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID

UG861

Release Date

2026-04-28

Revision

1.1 English

The following figure shows a sample circuit illustrating a board topology for differential HSUL_12 with unidirectional signaling.

Figure 1. Differential HSUL_12 with Unidirectional Signaling

The following figure shows a sample circuit illustrating a board topology for differential HSUL_12 with unidirectional DCI signaling.

Figure 2. Differential HSUL_12 with Unidirectional DCI Signaling

The following figure shows a sample circuit illustrating a board topology for differential HSUL_12 with bidirectional signaling.

Figure 3. Differential HSUL_12 with Bidirectional Signaling

The following figure shows a sample circuit illustrating a board topology for differential HSUL_12 with bidirectional DCI signaling.

Figure 4. Differential HSUL_12 with DCI Bidirectional Signaling

The following table lists the allowed attributes for HSUL I/O standards. Support is implied for primitives that are derivatives of the primitives listed in the following table (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to SelectIO IOB Interface Primitives for all supported derivatives.

Table 1. HSUL Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O		HP and XP5IO I/O		HD I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	HSUL_12 DIFF_HSUL_12		HSUL_12 DIFF_HSUL_12		HSUL_12 DIFF_HSUL_12		N/A		HSUL_12 DIFF_HSUL_12		N/A
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW	FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW
ODT	RTT_120 RTT_240 RTT_NONE	RTT_NONE	N/A		N/A		N/A		RTT_120 RTT_240 RTT_NONE	RTT_NONE	N/A
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A
Applies to DIFF_HSUL12 I/O standards.

Table 2. HSUL Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP I/O		HD and XP5IO I/O		HP I/O		HD and XP5IO I/O		HP I/O		HD and XP5IO I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	HSUL_12_DCI DIFF_HSUL_12_DCI		N/A		HSUL_12_DCI DIFF_HSUL_12_DCI		N/A		HSUL_12_DCI DIFF_HSUL_12_DCI		N/A
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	N/A		FAST MEDIUM SLOW	SLOW	N/A
DQS_BIAS¹	TRUE FALSE	FALSE	N/A		N/A		N/A		TRUE FALSE	FALSE	N/A
ODT	RTT_120 RTT_240 RTT_NONE	RTT_NONE	N/A		N/A		N/A		RTT_120 RTT_240 RTT_NONE	RTT_NONE	N/A
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A
Applies to DIFF_HSUL12 I/O standards.