Differences from Previous Generations - Differences from Previous Generations - UG861

Spartan UltraScale+ devices support many of the same features supported in 7 series devices. However, there are some useful new features, along with changes to several existing features. These new features and changes for HP I/O, HD I/O, and XP5IO I/O include:

• Each HP I/O bank contains 52 SelectIO interface pins, HD I/O banks contain 42 SelectIO interface pins, and XP5IO I/O banks contain 66 SelectIO interface pins.
• HP and XP5IO I/O banks support pseudo-open-drain (POD) logic standards.
• Series output termination control is available in HP and XP5IO I/O banks for improved signal integrity and ease of board design.
• Internal or external V_REF is available in HP I/O banks, while only internal V_REF is available in HD and XP5IO I/O banks.
• Pre-emphasis is available for several standards in HP and XP5IO I/O banks. Pre-emphasis reduces inter-symbol interference and minimizes the effects of transmission line losses.
• Linear equalization on several V_REF-based standards (in HP and XP5IO I/O banks) is available to overcome high-frequency losses through the transmission channel.
• Receiver offset cancellation is available for some I/O standards to compensate for process variations (HP I/O banks only).
• Digitally controlled impedance (DCI) is available in HP and XP5IO I/O banks. DCI requires one reference resistor per bank in HP and one per device in XP5IO. The values of the driver or input termination are determined by the OUTPUT_IMPEDANCE and on-die termination (ODT) attributes, respectively.
• Uncalibrated ODT (input termination) is available in both HP and HD I/O banks.
• A SLEW value of MEDIUM is supported in HP and XP5IO I/O banks in addition to FAST and SLOW which are supported in all three banks.
• The DCITERMDISABLE port can control both DCI and non-DCI on-die input termination features in HP and XP5IO I/O banks.
• Asserting IBUFDISABLE on HP I/O pins and HD I/O pins causes the input to the interconnect logic to be a 0. This is different from the resulting 1 after asserting IBUFDISABLE on XP5IO I/O pins and in 7 series devices.
• In HP I/O, the bit slice is effectively a physical layer (PHY) block that replaces and enhances the functionality of the component mode primitives. This PHY block gives tighter control over timing and provides new features enabling higher data rate reception in UltraScale+ devices. See Native Primitives.
• MIPI D-PHY transmitter and receiver functions are supported in the HP and XP5IO I/Os.
• XP5IO I/O banks have eleven PHY nibbles that enable high-speed interfaces to support MIPI D-PHY and LPDDR5.
• XP5IO I/O banks add LVSTL support to enable LPDDR5 interfaces.