Differences Between Bank Types - Differences Between Bank Types - UG861

As noted in I/O Tile Overview, the Spartan UltraScale+ family consists of three different SelectIObank types: HP I/O, HD I/O, and XP5IO I/O. The bank types are optimized with different features, supply levels, applications, and performance levels. The following descriptions call out fundamental differences in the bank type to help define an appropriate bank type selection for a given application.

HP I/O Bank

The HP I/O bank is intended for higher performance interfaces that are powered from 1.0V to 1.8V. This includes higher performance interface standards like LVDS, POD, SSTL, and MIPI D-PHY. The HP I/O banks have basic register resources but also contain a PHY with a robust feature set that helps accommodate high-performance fourth generation memory interfaces as well as high-performance MIPI D-PHY interfaces. The HP I/O bank supports high-speed interfaces by leveraging several features: a dedicated PHY with clock-data phase alignment features, calibrated internal termination, receive CTLE equalization, pre-emphasis, and support for several I/O standards used in DDR4/LPDDR4 memory, as well as MIPI D-PHY.

HD I/O Bank

The HD I/O bank is primarily intended to accommodate lower-speed interfaces that might require basic register function with a wide range of voltage support levels (1.2V to 3.3V). The HD I/O banks support basic SDR/DDR dedicated registers, uncalibrated termination, and zero hold (ZHOLD) which can be used to preserve clock alignment.

XP5IO Bank

The XP5IO bank is unique to the Spartan UltraScale+ architecture and is present in several devices. It operates at a supply range between 1.0V and 1.5V and adds LPDDR5 interface support to the Spartan UltraScale+ family . In addition, the XP5IO contains a dedicated PHY which can be used for source-synchronous applications like MIPI D-PHY. XP5IO banks are intended for high-speed PHY operation such as MIPI D-PHY and LPDDR5 interfaces. As a result, there are no IOL resources like IDDR, ODDR, or IODELAY, though the PHY can be bypassed to access fabric resources from the IOB.