DQS_BIAS in HP I/O Banks - DQS_BIAS in HP I/O Banks - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

DQS_BIAS provides a logic holding mechanism for undriven pins in pseudo-differential (DIFF_SSTL, DIFF_HSUL, and DIFF_POD) buffers by weakly pulling the N side of the buffer to VCCO and the P side of the buffer to ground. For LVDS inputs in HP I/O banks, the DQS_BIAS attribute can also be used to provide a DC bias of VCCO/2 to both the P and N sides of the buffer.

The allowed values for the DQS_BIAS attribute for applicable I/O standards are:

  • TRUE where DQS_BIAS = TRUE cannot be used with the PULLTYPE attribute set to PULLUP, PULLDOWN, or KEEPER in the same port.
  • FALSE (default)

The DQS_BIAS attribute should be set on the port using the syntax:

set_property DQS_BIAS TRUE|FALSE [get_ports port_name ]