DCI I/O Standard Support - DCI I/O Standard Support - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

DCI supports the standards shown in the following table.

Table 1. All Supported DCI I/O Standards in HP I/O Banks
LVDCI HSTL/DIFF_HSTL SSTL/DIFF_SSTL POD/DIFF_POD HSUL/DIFF_HSUL
LVDCI_18 HSTL_I_DCI SSTL18_I_DCI POD12_DCI HSUL_12_DCI
LVDCI_15 HSTL_I_DCI_18 SSTL15_DCI POD10_DCI DIFF_HSUL_12_DCI
HSLVDCI_18 DIFF_HSTL_I_DCI SSTL135_DCI DIFF_POD12_DCI  
HSLVDCI_15 DIFF_HSTL_I_DCI_18 SSTL12_DCI DIFF_POD10_DCI  
    DIFF_SSTL18_I_DCI    
    DIFF_SSTL15_DCI    
    DIFF_SSTL135_DCI    
    DIFF_SSTL12_DCI    
Table 2. All Supported DCI I/O Standards in XP5IO I/O Banks
HSTL/DIFF_HSTL SSTL/DIFF_SSTL LVDCI/HSLVDCI HSUL/DIFF_HSUL POD/DIFF_POD LVSTL/DIFF_LVSTL
HSTL_I SSTL15 LVDCI_15 HSUL_12 POD12 LVSTL06_12
HSTL_I_12 SSTL135 HSLVDCI_15 DIFF_HSUL_12 POD10 LVSTL_11
DIFF_HSTL_I SSTL12     DIFF_POD12 LVSTL05_10
DIFF_HSTL_I_12 DIFF_SSTL15     DIFF_POD10 DIFF_LVSTL06_12
  DIFF_SSTL135       DIFF_LVSTL_11
  DIFF_SSTL12       DIFF_LVSTL05_10

To correctly use DCI:

  1. VCCO pins must be connected to the appropriate VCCO voltage based on the I/O standards in that I/O bank.
  2. Correct DCI I/O buffers must be used in the Vivado Design Suite either by using I/O standard attributes or instantiations in the hardware description language (HDL) code. For HP I/O banks, the Vivado Design Suite automatically restricts the VRP pin from being used as an I/O when a VRP needs to be used as a reference.
  3. DCI standards require connecting an external reference resistor to the multipurpose VRP/VR pin. In HP I/O banks, when this is required, that multipurpose pin cannot be used as a general-purpose I/O in the I/O bank using DCI or in the master I/O bank when cascading DCI. See the pinout tables for the specific pin locations. The VRP pin must be pulled to GND by a reference resistor. An exception to this requirement comes when cascading DCI in slave I/O banks because the VRP pin can be used as general-purpose I/O. XP5IO banks VR pins are dedicated and MUST always be terminated to VCCO
  4. The value of the external reference resistor is fixed at 240 Ω, terminated to GND for HP I/O and to VCCO for XP5IO banks.
  5. Follow the DCI I/O banking rules:
    1. In HP I/O banks, VREF must be compatible for all of the inputs in the same I/O bank or in a group of I/O banks when using DCI cascade.
    2. VCCO must be compatible for all of the inputs and outputs in the same I/O bank.