Controlling IBUF_DISABLE and DYN_DCI - Controlling IBUF_DISABLE and DYN_DCI - UG861

IBUF_DISABLE and DYN_DCI are signals used for power saving. By connecting these signals to an applicable buffer, the buffer and/or DCI can be turned off, resulting in power savings. The behavior of IBUF_DISABLE and DYN_DCI is dependent upon:

1. ODT_SRC_# attribute
2. IBUF_DIS_SRC_# attribute

The following table shows the behavior of IBUF_DISABLE and DYN_DCI. DYN_DCI is expected to be connected to DCITERMDISABLE of the buffer (so DYN_DCI being 1 turns off ODT), and IBUF_DISABLE is expected to be connected to IBUFDISABLE of the buffer (so IBUF_DISABLE being 1 turns off the receiver) when using the PL for control.

When Controlled from the PL is listed, the I/O primitive controls the functionality. For example, on the IOBUFE3, the IBUFDISABLE can disable the input buffer to save power. Similarly, DCITERMDISABLE controls ODT. IBUFDISABLE and DCITERMDISABLE are automatically routed through the XP5PHY_LS and XP5PHY_HS to connect to the fabric.

When PHY_SM controlled is listed, the XP5IO PHY state machine (SM) controls DYN_DCI or IBUF_DISABLE. The state machine operates as follows:

1. Transitions from 1 to 0 after two cycles (with frequency equal to PLL_CLK/RX_DATA_WIDTH) after PHY_RDEN is asserted
2. Stays 0 for a programmable number of cycles after PHY_RDEN is deasserted (determined by the RD_IDLE_COUNT register and the clock being the same as the aforementioned clock)
3. After the wait, transitions from 0 to 1