Component Primitives - Component Primitives - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document_ID: UG861
Release_Date: 2026-04-28
Revision: 1.1 English

SelectIO Interface Resource Overview
Introduction to the UltraScale Architecture
I/O Tile Overview
Differences from Previous Generations
Differences Between Bank Types
SelectIO IOB Technology and Supported Standards
SelectIO Interface General Guidelines
I/O Bank Rules
Supply Voltages for the SelectIO Pins
VCCO
VREF
VCCAUX_IO, VCCAUX_HDIO, VCCAUX_HPIO, and VCCAUX_XP5IO
VCCINT_HPIO and VCCINT_XP5IO
State of I/Os During and After Configuration
DCI in the HP I/O and XP5IO I/O Banks
Introduction
Match_cycle Configuration Option
DCIUpdateMode Configuration Option
DCIRESET Primitive
Controlled Impedance Driver (Source Termination)
Split-Termination DCI (Thevenin Equivalent Termination to VCCO/2)
Single-Termination DCI
VRP External Resistance Design Migration Guidelines
T_DCI Design Migration Guidelines
DCI I/O Standard Support
Uncalibrated Input Termination in HP and HD I/O Banks
Uncalibrated Source Termination in HP I/O Banks
Receiver Offset Control in HP I/O Banks
Internal VREF in HP I/O Banks
SelectIO IOB Interface Primitives
IBUF
IBUF_IBUFDISABLE and IBUF_IBUFDISABLE_XP5
IBUF_INTERMDISABLE
IBUFE3 and IBUFE3_XP5
IBUFDS
IBUFDS_DIFF_OUT
IBUFDS_DIFF_OUT_IBUFDISABLE and IBUFDS_DIFF_OUT_IBUFDISABLE_XP5
IBUFDS_DIFF_OUT_INTERMDISABLE
IBUFDS_IBUFDISABLE and IBUFDS_IBUFDISABLE_XP5
IBUFDS_INTERMDISABLE
IBUFDSE3 and IBUFDSE3_XP5
IBUFDS_DPHY
IOBUF
IOBUF_DCIEN
IOBUF_INTERMDISABLE
IOBUFE3
IOBUFDS
IOBUFDS_DCIEN and IOBUFDS_DCIEN_XP5
IOBUFDS_DIFF_OUT and IOBUFDS_DIFF_OUT_XP5
IOBUFDS_DIFF_OUT_DCIEN
IOBUFDS_INTERMDISABLE
IOBUFDS_DIFF_OUT_INTERMDISABLE
IOBUFDSE3 and IOBUFDSE3_XP5
OBUF
OBUFDS
OBUFT
OBUFTDS
OBUFDS_DPHY
HPIO_VREF and XP5IO_VREF
SelectIO Interface Attributes and Constraints
PACKAGE_PIN Constraint
IOSTANDARD Attribute
IBUF_LOW_PWR Attribute (HP and XP5IO I/O Banks Only)
Output Slew Rate Attributes
Output Drive Strength Attributes
PULLTYPE Attribute
On-Die Termination (ODT) Attribute
Source Termination Attribute (OUTPUT_IMPEDANCE)
Differential Termination Attribute
Internal VREF
DQS_BIAS in HP I/O Banks
DC_BIAS in XP5IO I/O banks
Transmitter Pre-Emphasis
LVDS Transmitter Pre-Emphasis
Receiver EQUALIZATION
Receiver OFFSET Control
VREF_CNTR
DATA_RATE
I/O Resource VHDL/Verilog Examples
Supported I/O Standards and Terminations
Low Voltage Transistor-Transistor Logic (LVTTL)
Low Voltage CMOS (LVCMOS)
LVDCI
HSLVDCI
High-Speed Transceiver Logic (HSTL)
HSTL_I and HSTL_ I_18
HSTL_I_12
HSTL_ I_DCI, HSTL_I_DCI_12, and HSTL_ I_DCI_18
DIFF_HSTL_I and DIFF_HSTL_I_18
DIFF_HSTL_I_DCI and DIFF_HSTL_I_DCI_18
DIFF_HSTL_I_12
DIFF_HSTL_I_12_DCI
HSTL Class I Termination
Differential HSTL Class I Termination
HSTL Allowed Attributes
Stub-Series Terminated Logic (SSTL)
SSTL18_I, DIFF_SSTL18_I
SSTL18_I_DCI, DIFF_SSTL18_I_DCI
SSTL15, SSTL135, SSTL12, DIFF_SSTL15, DIFF_SSTL135, DIFF_SSTL12
SSTL15_DCI, SSTL135_DCI, SSTL12_DCI, DIFF_SSTL15_DCI, DIFF_SSTL135_DCI, DIFF_SSTL12_DCI
SSTL18, SSTL15, SSTL135, SSTL12 Termination
Differential SSTL18, SSTL15, SSTL135, SSTL12 Termination
High Speed Unterminated Logic (HSUL_12)
HSUL_12 and DIFF_HSUL_12
HSUL_DCI_12 and DIFF_HSUL_12_DCI
HSUL_12 Termination
Differential HSUL_12 Termination
Pseudo Open Drain (POD)
POD10, POD12, DIFF_POD10, and DIFF_POD12
POD10_DCI, POD12_DCI, DIFF_POD10_DCI, and DIFF_POD12_DCI
POD Termination
Differential POD Termination
Low-voltage Differential Signaling (LVDS)
Receiver Termination (HP and XP5IO I/O Banks Only)
Low-Voltage Swing Terminated Logic (LVSTL)
Sub-Low Voltage Differential Signaling (SUB_LVDS)
Scalable Low Voltage Signaling (SLVS_400)
Low Voltage Positive Emitter-Coupled Logic (LVPECL)
Mobile Industry Processor Interface Display Physical Layer (MIPI D-PHY)
MIPI_DPHY and MIPI_DPHY_DCI I/O Standard
Internal Differential Termination Behavior in Differential I/O Standards in HP I/O Banks
Rules for Combining I/O Standards in the Same Bank
Simultaneous Switching Outputs
Pin Planning to Mitigate SSO Sensitivity
HP I/O Bank SelectIO Interface Logic Resources
HP I/O Bank Overview
Component Primitives
Simple Registered Inputs and Outputs
IDDRE1
OPPOSITE_EDGE Mode
SAME_EDGE Mode
SAME_EDGE_PIPELINED Mode
IDDRE1 Ports
IDDRE1 Attributes
ODDRE1
ODDRE1 Ports
ODDRE1 Attributes
ODDR with Serialized 3-State
ISERDESE3
ISERDESE3 Ports
ISERDESE3 Attributes
OSERDESE3
OSERDESE3 Ports
OSERDESE3 Attributes
IDELAYE3
IDELAYE3 Ports
IDELAYE3 Attributes
DELAY_SRC Attribute
CASCADE Attribute
DELAY_FORMAT Attribute
DELAY_VALUE Attribute
UPDATE_MODE Attribute
DELAY_TYPE Attribute
FIXED Mode
VARIABLE Mode
VAR_LOAD Mode
ODELAYE3
ODELAYE3 Ports
ODELAYE3 Attributes
CASCADE Attribute
DELAY_FORMAT Attribute
DELAY_VALUE Attribute
UPDATE_MODE Attribute
DELAY_TYPE Attribute
FIXED Mode
VARIABLE Mode
VAR_LOAD Mode
IDELAYCTRL
IDELAYCTRL Ports
Component Mode Reset Sequence
Apply Reset
Release Reset
Clocking Considerations Using Component Primitives
Bidirectional Signaling Using Component Mode
Mixing Native and Non-Native Mode I/O in a Nibble
Native Primitives
RXTX_BITSLICE
Input and Output Delay Lines
Delay Line Cascading
3-State Control
FIFO
RXTX_BITSLICE Receiver Function
Receiver Setup
Calculation of Required Frequencies
Native Input Delay Type Usage
FIXED Mode
VARIABLE Mode
VAR_LOAD Mode
FIFO Function
RXTX_BITSLICE Transmitter Function
Transmitter Setup
Native Output Delay Type Usage
FIXED Mode
VARIABLE Mode
VAR_LOAD Mode
RXTX_BITSLICE Ports
RXTX_BITSLICE Attributes
IS_…_INVERTED Attributes
RX_BITSLICE
RX_BITSLICE Function
RX_BITSLICE Ports
RX_BITSLICE Attributes
Extended Delay Control Signals
TX_BITSLICE
TX_BITSLICE Function
TX_BITSLICE Ports
TX_BITSLICE Attributes
TX_BITSLICE_TRI
TX_BITSLICE_TRI Function
TX_BITSLICE_TRI Ports
TX_BITSLICE_TRI Attributes
BITSLICE_CONTROL
BITSLICE_CONTROL Ports
BITSLICE_CONTROL Attributes
Native Mode Bring-up and Reset
Release Reset
Apply Reset
Bring-up for an Interface Using Multiple Banks
Bring-up for Multiple Interfaces in a Shared Bank
Clocking in Native Mode
Receive Clocking
Transmit Clocking
Inter-Nibble Clocking
Inter-Byte Clocking
Inter-byte Clocking Precautions
Built-in Self-Calibration
Ports and Attributes Influencing BISC
BISC Calibration Steps
Step 1: Alignment
Step 2: Delay Calibration
Step 3: Continuous VT Tracking
Register Interface Unit (RIU)
RIU Write Actions
RIU Read Actions
RIU Ports
Register Definitions and Addresses
HD I/O Interface Logic Resources
ZHOLD
DDR Inputs (IDDRE1)
DDR Outputs (ODDRE1)
XP5IO I/O Interface Logic Resources
XP5IO PHY Nibble
Controlling IBUF_DISABLE and DYN_DCI
XP5PHY_LS Ports
XP5PHY_LS Attributes
XP5PHY_HS Ports
Termination Options for Simultaneous Switching Noise Analysis
Termination Options
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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