Example 1
- Source synchronous DDR interface (data+clock) at 1250
Mb/s.
- RX_DATA_TYPE = DATA_AND_CLOCK for the bit slice receiving the forwarded clock
- With 1250 Mb/s comes a forwarded clock of 625 MHz.
- This clock is used to capture the data bits. Continuous clocks can optionally be used as PLL clock inputs.
- BITSLICE_CONTROL needs a PLL_CLK clock equal to the data
rate of the received signals.
- The PLL must deliver a 1250 MHz clock to the BITSLICE_CONTROL.
- The receiver used in 8-bits requires a FIFO_RD_CLK shown in
the following equation:forwarded clock / 4 = 156.25 MHz
- The receiver used in 4-bits requires a FIFO_RD_CLK shown in the following
equation:forwarded clock / 2 = 312.5 MHz
Example 2
- Asynchronous interface (data only) at 1250 Mb/s.
- RX_DATA_TYPE = SERIAL
- Clock needs to be delivered by PLL or MMCM.
- To sample 1250 Mb/s data, a DDR clock of 625 MHz is
required.
- The PLL/MMCM must deliver a 625 MHz clock to the BITSLICE_CONTROL.
- The receiver used in 8-bits requires a FIFO_RD_CLK shown in
the following equation:DDR (PLL/MMCM) clock / 4 = 156.25 MHz
- The receiver used in 4-bits requires a FIFO_RD_CLK shown in the following
equation:DDR (PLL/MMCM) clock / 2 = 312.5 MHz