CASCADE Attribute - CASCADE Attribute - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The CASCADE attribute is set to NONE if the delay line is not cascaded. Cascading is used when a delay greater than 1.10 ns is required. The connections between delay elements are shown in the following figure. When using the IDELAYE3 (or ODELAYE3) for cascading, the delay (and the IOB) are no longer available to the design. The delay elements can be cascaded up to the byte boundary in a downward direction. Therefore, the maximum possible length of the delay depends on where the I/O is placed in the byte.

The routes used to cascade IDELAYE3 and ODELAYE3 are dedicated, high-speed routes. The total fixed intrinsic insertion delay for an IDELAYE3 or ODELAYE3 cascade is the sum of the initial insertion delay plus the cascaded insertion delay. This delay grows as multiple of the times that IDELAYE3 and ODELAYE3 are cascaded. However, the delay is always a fixed value.

Figure 1. IDELAYE3 Cascading to Three Slave Delays

If cascading to achieve a delay > 1.10 ns with a DELAY_FORMAT = TIME, delays in the same site must have an equal delay. For example, a delay of 1.5 ns is split between a 0.75 ns IDELAYE3 and a 0.75 ns ODELAYE3. If cascading with IDELAYE3 and ODELAYE3 used in VAR_LOAD mode, the values are entered for both components separately. VAR_LOAD is discussed in DELAY_TYPE Attribute.