Bidirectional Signaling Using Component Mode - Bidirectional Signaling Using Component Mode - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

All 52 pins in a bank are capable of bidirectional operation using the same component primitives.

For bidirectional signaling with 3-state support, for the output and 3-state path use the solutions as discussed in ODDRE1. Note the 3-state path driving the T input for the IOBUF does not support simple registered outputs such as FDCE/FDPE/FDRE/FDSE. Registers for FDCE/FDPE/FDRE/FDSE for the 3-state path are implemented in internal logic.

For designs using an OSERDES, the following figure shows an example bidirectional pin with IDELAY and ODELAY. The OSERDES only supports combinatorial 3-state controls for the T input of the IOBUF.

Figure 1. Bidirectional Signaling Using IDELAY/ODELAY with ISERSDES and OSERDES
Note: When using bidirectional interfaces, the delay cascades are not available. For all other solutions, Native Primitives must be used.

Bidirectional support varies by I/O bank. The following table lists the recommended bidirectional logic. When unsupported, the Vivado tool can borrow resources from additional I/Os.

Table 1. Bidirectional Support by I/O Bank
Input Datapath Output Datapath Tristate Control I/O Banks
Fabric Logic Fabric Logic Fabric Logic HDIO/HPIO
IFD OFD Fabric Logic HDIO/HPIO
IFD OFD OFD HDIO
IDDRE1 ODDRE1 Fabric Logic HPIO
IDDE1 ODDRE1 ODDRE1 HPIO
ISERDES3 OSERDESE3 Fabric Logic HPIO
ISERDES3 OSERDESE3 OSERDESE3 Not supported