BITSLICE_CONTROL Attributes - BITSLICE_CONTROL Attributes - UG861

TRUE

FALSE

Enable inter-nibble clocking.

When set to TRUE, the PCLK is sourced from the other BITSLICE_CONTROL in the byte.

If this is turned on for one BITSLICE_CONTROL, it cannot be turned on for the other BITSLICE_CONTROL in the same byte.

TRUE

FALSE

Enable inter-nibble clocking. When set to TRUE, the NCLK is sourced from the other BITSLICE_CONTROL in the byte.

If this is turned on for one BITSLICE_CONTROL, it cannot be turned on for the other BITSLICE_CONTROL in the same byte.

TRUE

FALSE

When set to TRUE, the master input clock, PLL_CLK or REFCLK, and the divided versions are used as the sample clock for the deserializer of a bit slice.

When set to FALSE, the clock or strobe applied to a BITSLICE_0 is used as sample clock.

When only data or data with embedded clock are applied to bit slices, use the SERIAL_MODE. The main function of the bit slices is to sample an incoming data stream with a clock generated from an internal, unrelated to the data source, such as a PLL.

Shifts the P-edge of the read clock by 0 degrees or 90 degrees relative to the captured data.

Data is sampled by a clock in the middle of a bit period. When clock and data arrive at the pin phase-aligned, use a shift by 90 degrees, or else leave this attribute at the default value.

When using SHIFT_90, DELAY_VALUE (RX_BITSLICE) or RX_DELAY_VALUE (RXTX_BITSLICE) must be 0.

Shifts the N-edge of the read clock by 0 degrees or 90 degrees relative to the captured data.

Data is sampled by a clock in the middle of a bit period. When clock and data arrive at the pin phase-aligned, use a shift by 90 degrees, or else leave this attribute at the default value.

When using SHIFT_90, DELAY_VALUE (RX_BITSLICE) or RX_DELAY_VALUE (RXTX_BITSLICE) must be 0.

TRUE

FALSE

DISABLE

ENABLE

Write clock gating. For aligned transmitted data, TX_GATING must set to ENABLE and control the TBYTE_IN from interconnect logic.

Read Native Mode Bring-up and Reset for more information.

When TX_GATING = ENABLE, TBYTE_IN[3:0] is used to stop the clock for transmit interfaces.

Enables read strobe/clock gating.

The value of this attribute and the mechanism behind it is to gate in the strobe/clock during its preamble. Gate off the strobe/clock immediately following each of its falling edges and enable it afterward.

The gating circuit used by the attribute is only available in BITSLICE_0 of a nibble because strobe/clock can only be input from the BITSLICE_0 location in a nibble.

When set to TRUE, the gate is controlled by the BITSLICE_CONTROL.PHY_RDEN input.

Number of clocks after PHY_RDEN deassertion and before turning off ODT termination.

MIG USE ONLY.

DIV2

DIV4

Determines how the master clock is divided.

When 8-bit mode is used (1:8 serial input), set to DIV4.

When 4-bit mode is used, set to DIV2. The FIFO_WRCLK_OUT clock reflects the action of this attribute.

When the master clock is the PLL_CLK, this attribute should be set to PLLCLK.

When the master clock is the REFCLK input (RX_BITSLICE only), this attribute must be set to REFCLK.

Rounding factor for BISC.

MIG USE ONLY.

TRUE

FALSE

Built-in self-calibration (BISC) enable.

When set to ENABLE, BISC runs initial calibration after release of reset.

When set to DISABLE, calibration is not run after release of reset.

TRUE

FALSE

TRUE

FALSE

TRUE

FALSE

TRUE

FALSE