Apply Reset - Apply Reset - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English
  1. The EN_VTCs are High for all of the USED IDELAYs and ODELAYs.
  2. Assert Reset to the PLL/MMCM, which generates the clock for IDELAY and IDELAYCTRL.
  3. Apply Reset to IDELAYCTRL, IDELAY TIME mode, ISERDES, OSERDES, and ODELAY TIME mode.
  4. Wait the minimum PLL/MMCM reset assertion time before releasing the reset. For this timing specification, consult the PLL/MMCM section of the UltraScale device data sheets in the references section.