Apply Reset - Apply Reset - UG861

1. Assert reset to the PLL.
2. Apply reset to RXTX_BITSLICE.TX_RST_DLY, RXTX_BITSLICE.RX_RST_DLY, TX_BITSLICE_TRI.RST_DLY, RXTX_BITSLICE.TX_RST, RXTX_BITSLICE.RX_RST, TX_BITSLICE_TRI.RST, and/or BITSLICE_CONTROL.RST.
3. Stop strobe clocks.
4. Wait the minimum PLL reset assertion time before releasing the reset. For this timing specification, consult the PLL section of the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) . Then follow the steps in Native Mode Bring-up and Reset for correct bring-up.