Status Register Use and JTAG Access - Status Register Use and JTAG Access - UG860

In addition to the status pins there are several key status registers that can be accessed through the JTAG interface. The Spartan UltraScale+ FPGA JTAG registers that provide valuable data for debug include:

• IDCODE
• JTAG_STATUS
• ERROR_STATUS
• FW_STATUS

AMD Vivado Design Suite device programmer captures the IDCODE and status registers information when connected to the Spartan UltraScale+ FPGA device. The status registers contain information about power rail levels, status pins (DONE pin, INIT_B pin) and mode pin settings. The status registers also provide SelectMAP bus width and correctable and non-correctable error codes.