At the end of Phase 3, after the PDI contents have been loaded to the programmable logic (PL) configuration frames the device enters a start-up sequence. The start-up sequence has steps (0-7), shown in Figure 1. The start-up sequence is on the CCU clock domain and performs the tasks outlined in the following table.
| Step | Event |
|---|---|
| 1-6 | Wait for MMCMs to lock (optional) |
| 1-6 | Wait for DCI to match (optional) |
| 1-6 | Assert global write enable (GWE), allowing RAMs and flip-flops to change state |
| 1-6 | Negate global 3-state (GTS), activating I/O |
| 1-6 | Release DONE pin |
| 7 | Assert end of start-up (EOS) |
| Step | Event |
|---|---|
| 4 | Release DONE pin |
| 5 | Negate Global 3-State (GTS), activating I/O |
| 6 | Assert GWE, allowing RAMs and flip-flops to change state |
| 7 | Assert End Of Start-up (EOS) |
The start-up sequence can be forced to wait for the MMCMs to lock or the DCI to match with the appropriate PDI options. These options are typically set to prevent the DONE, GTS, and GWE from being asserted before the MMCMs have locked and/or DCI has matched. The start-up sequence steps are part of the Phase 3 which includes steps in the configuration through the start-up shown in the following figure.
Figure 1. Configuration Signal Sequencing (Default Start-Up
Settings)
