Slave Modes - Slave Modes - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)

Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English

The externally controlled loading FPGA slave configuration modes, generically called slave modes, are also available with either a serial or parallel data path. In slave mode, an external processor, microcontroller, DSP processor, or tester downloads the configuration image into the FPGA, as shown in the following figure. The advantage of the slave configuration modes is that the FPGA PDI can reside almost anywhere in the overall system. The PDI can reside in flash along with the host processor's code, on a hard disk, or over a network connection.

Figure 1. Slave Configuration Modes

The Spartan UltraScale+ FPGA slave serial mode is a simple interface that consists of a clock, serial data input, chip-select input, and a READY monitor output. The Slave SelectMAP mode is an 8, 16, or 32-bit wide data interface that includes a chip-select input, a read/write control input, and a BUSY monitor signal.