Serial x1 Configuration Interface Example - Serial x1 Configuration Interface Example - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)
Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English
Slave serial configuration is typically used for devices in a serial daisy chain or when configuring a single device from an external microprocessor (see the following figure). The READY signal can be deasserted at any stage during configuration, so this signal must be monitored to ensure that the interface is ready to accept data (READY=1). When the READY signal is deasserted it indicates that the FPGA data loading must be paused. The chip select input (CS_B) must be deasserted within 24 CCLK clock cycles to handle the data load stream without error.
Figure 1. Serial x1 Configuration Interface Example

Figure Notes:

  1. The DONE pin is by default an open-drain output. An external pull-up resistor is required.
  2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.
  3. CCLK signal integrity is critical.
  4. See the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) for the VCCINT, VCCAUX, and VCCO_0 supply voltages.
  5. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to VCCO_0 to 3-state the SelectIOpins after power-up and during configuration.
Note: See Table 1 under Configuration Pins for signal details.