Serial Mode Sequence - Serial Mode Sequence - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)
Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English

The Serial interface allows an external processor to load the configuration data. The functional waveform in this section shows an example of the Serial interface data, clock, and control signals sequence used to load data into the Spartan UltraScale+ FPGAs. To configure the device in the Serial configuration mode, ensure that the dedicated boot mode pins are set to Serial (MODE[2:0])=111. The device samples the Serial DIN and clocks the READY on the rising CCLK edges. The waveform shows an example READY response. When the READY signal is deasserted, the CS_B signal must be deasserted within 24 CCLK cycles. Deasserting the CS_B will pause the PDI load until the READY signal is asserted again indicating the device is ready to receive data.

Figure 1. Serial x1 Data Loading
Figure Notes:
  1. After READY is asserted and INIT_B is deasserted, the user can start data loading.
  2. When READY is deasserted during Serial data loading, the CS_B must be deasserted within 24 CCLK cycles.
  3. After the last data byte is sent, deassert CS_B. The time that it takes for DONE to transition high will be design dependent. If the design is configured to include ECC protected DDR memory, the DONE transition time can take up to 2 seconds.