The SelectMAP interface allows an external processor to load the
configuration data. The functional waveform in this section shows an example of the
SelectMAP interface data, clock, and control signals sequence used to load data into
the FPGAs. To configure the device in SelectMAP, ensure that the dedicated boot mode
pins are set to SelectMAP (MODE[2:0])=110 and
RDWR_B=0). The device samples the SelectMAP
datapins on the rising CCLK edges and the BUSY signal is also clocked by the CCLK. The waveform shows the 16 byte bus detect
pattern for the SelectMAP boot mode. The waveform shows an example BUSY response. When the BUSY signal is asserted, the CSI_B
signal must be deasserted within 24 CCLK
cycles.
Figure Notes:
- After
INIT_BandBUSYare deasserted, the user can start data loading. - The SelectMAP bus detect pattern is the first 16 bytes of
the PDI. The
JTAG_STATUS [5:4]SelectMAP bus width field is updated when this pattern is read by the BootROM. - When
BUSYis asserted during SelectMAP data loading, theCSI_Bmust be deasserted within 24CCLKcycles (CSMAPBUSYCS). - After the last data byte is sent, deassert
CSI_B. The time that it takes for DONE to assert will be design dependent. If the design is configured to include ECC protected DDR memory, the DONE transition time can take up to 2 seconds.