One or more devices can be configured through the SelectMAP bus.
In the SelectMAP configuration mode there are multiple host options that can
configure the Spartan UltraScale+ FPGA.
For a typical setup, a processor provides data (D[31:00]) and clock (CCLK)
inputs to one or multiple FPGAs on the data bus, the processor controls the chip
select (CSI_B) input to select which FPGA to
configure, and monitors the BUSY signal. The
bus width in Slave SelectMAP configuration mode is automatically detected by the
internal configuration logic and firmware.
Spartan
UltraScale+ FPGA
devices include a BUSY pin on the protocol
interface that is not required on the other UltraScale+ FPGA devices. For Spartan
UltraScale+
devices, the BUSY pin can be asserted at any
stage during configuration and must be monitored to ensure that the interface is
ready to accept data. When the BUSY signal is
asserted it indicates that the FPGA data loading must be paused. The chip select
input (CSI_B) must be deasserted to pause the
data loading.
The SelectMAP configuration interface pins shown in the following figure are defined in Table 1.
