The Spartan UltraScale+
FPGA SelectMAP interface provides continuous data loading. Data loading is controlled by
the BUSY (monitor signal), CSI_B, RDWR_B, and CCLK signals.
CSI_B
The chip select input (CSI_B)
enables the SelectMAP bus. When CSI_B is High, the
FPGA ignores the SelectMAP interface, neither registering any inputs nor driving any
outputs. The D[31:00] pins are placed in a 3-state,
and RDWR_B is ignored.
- If
CSI_B= 0, the device's SelectMAP interface is enabled. - If
CSI_B= 1, the device's SelectMAP interface is disabled.
RDWR_B
RDWR_B is an input to the FPGA that
controls the data path for write control. For configuration, RDWR_B must be set for write control (RDWR_B =
0). Slave SelectMAP solution readback support is not available in Spartan
UltraScale+.
CCLK
All activity on the SelectMAP data bus is synchronous to CCLK. When RDWR_B is
set for write control (RDWR_B = 0, configuration),
the FPGA samples the SelectMAP data pins on rising CCLK edges.
BUSY
Busy active-High output asserts (BUSY=1) when the FPGA data loading must be paused. When BUSY asserts this indicates there are 24 CCLK clock cycles left before the internal
configuration logic overflows and is not able to handle the data load stream.
Spartan UltraScale+ FPGAs use the SelectMAP interface pins described for data loading. A functional waveform example of the SelectMAP data loading process is provided along with bus detection details in the following sections.