SelectMAP Bit Order - SelectMAP Bit Order - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)

Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English

The SelectMAP interface is typically driven by a user application residing on a microprocessor, microcontroller, or another FPGA or SoC. The Spartan UltraScale+ FPGA automatically detects the bus width during configuration. For these applications, it is valuable to understand how the data ordering in the programmable Spartan UltraScale+ device's image corresponds to the data ordering expected by the device's interface when debugging. The following table shows how to load the SelectMAP PDI data bits onto the SelectMAP data pins.

Table 1. SelectMAP PDI Bus Detection Pattern
SMAP Bus Width SMAP_CLK Cycle
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D[07:00] 0x00 0x00 0x00 0xDD 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xAA 0xBB 0xCC
D[15:00] 0x0000 0x00DD 0x1122 0x3344 0x5566 0x7788 0x99AA 0xBBCC                
D[31:00] 0x000000DD 0x11223344 0x55667788 0x99AABBCC                        
  1. Spartan UltraScale+ SelectMAP mode does not require bit-swapping the data from the programming image.