The STARTUPE3 primitive connects to the dedicated configuration pins
(located in bank 0). The primitive allows post-configuration control of the SPI (x1, x2, or
x4) flash device data pins D[03:00] and FCS_B. When the
flash device is only used for configuration, the FPGA design does not require the
STARTUPE3.
The SelectMAP configuration mode data pins D[32:04] and the OSPI configuration mode data pins OSPID[07:00] can be directly
connected as part of the user design because they are multi-function bank configuration
pins.
The STARTUPE3 is a superset of STARTUPE2, and designs are re-targeted
automatically. The STARTUPE3 primitive for the UltraScale
architecture-based FPGAs does not provide specification of the startup clock that was
available in the STARTUPE2 for 7 series. Instead, it includes the FCS_B and separate input and output
connections for the bidirectional D[03:00] pins.
The STARTUPE3 primitive KEYCLEARB signal is used as the security use case tamper_fabric_b signal because this family does not have BBRAM.