SPI x4 Configuration Interface Example - SPI x4 Configuration Interface Example - UG860

UltraScale FPGAs support a 4-bit (x4) quad SPI master configuration width as shown in the following figure.

Figure Notes:

1. The DONE pin is by default an open-drain output. An external pull-up resistor is required.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.
3. CCLK signal integrity is critical.
4. A series resistor should be considered for the datapath from the flash to the FPGA to minimize overshoot. The proper resistor value can be determined from simulation.
5. The FPGA V_{CCO_0} supply must be compatible with the V_CC for the I/O of the flash device.
6. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to VCCO_0 to 3-state the SelectIO pins after power-up and during configuration.
7. Dependent on the Bank 65 or Bank 66 is used for the multi-function configuration I/O.