SPI x1/x2 Configuration Interface Example - SPI x1/x2 Configuration Interface Example - UG860

The following figure shows the connections for a SPI configuration with a 1-bit or 2-bit data width. These connections are the same because the 2-bit mode uses the D[00] pin as a data In/Out pin. The data pins used only as FPGA inputs are shown as unidirectional in the figures, although in some cases they may be bidirectional before or after configuration. The FPGA pin connections to the SPI NOR flash involved in the master SPI mode are listed in Table 1 under Configuration Pins.

Figure 1. SPI x1/x2 Configuration Interface Example

Figure Notes:

1. The DONE pin is by default an open-drain output. An external pull-up resistor is required. See Table 1 for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required. See Table 1 for INIT_B signal details.
3. CCLK signal integrity is critical.
4. A series resistor should be considered for the data path from the flash to the FPGA to minimize overshoot. The proper resistor value can be determined from simulation.
5. The FPGA V_{CCO_0} supply must be compatible with the VCC for the I/O of the flash device.
6. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups, or it can be tied to V_{CCO_0} to 3-state the SelectIO pins after power-up and during configuration. See Table 1 for PUDC_B signal details.
7. Bank 65 or Bank 66 is used for the multi-function configuration I/O. See the Configuration Pins section for details.