Recommended Design Flow and Configuration Factors - Recommended Design Flow and Configuration Factors - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)

Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English

Although configuration is typically a one-time event independent of the FPGA operation, configuration choices can affect design options. Consider configuration decisions early in the design cycle to eliminate challenges late in your design cycle.

  • Determine which configuration mode is optimal based upon the system's characteristics.
  • Allow for JTAG configuration as an additional mode for debugging purposes.
  • Provide easy access to the configuration control and status pins for debugging.
  • Plan for the multi-function pins that are active during configuration and accordingly, check for conflicts with the other uses of these pins.
  • Provide quality signal integrity for key signals during PCB layout including the configuration clock, even though configuration can operate at a low frequency.
  • Consider all aspects of the configuration sequence to reduce configuration time, including the power-up time for the supplies.
  • Consider the variety of options when generating the configuration PDI and check for device operation conflicts.
  • Generate the configuration PDI using the latest version of the AMD tools targeting the version of the device that is used (ES or production).
Important: A programmable device image generated for an engineering sample should not be used in production devices. Production devices must always use PDI with the correct production device target.
  • Correct DRC errors and review any warnings when the configuration PDI is generated.