At power-on, the FPGA automatically starts its configuration procedure. When the FPGA is in SPI configuration mode, the FPGA asserts FCS_B Low to select the flash and drives a read command to the flash. The flash must be awake and ready to receive commands before the FPGA drives FCS_B Low and sends the read command. Because different power rails can supply the FPGA and flash or because the FPGA and flash can respond at different times along the ramp of a shared power supply, special attention to the FPGA and flash power-on sequence or power-on ramps is essential. For more information, see Power-On Sequence Precautions for Flash.