Power-On Sequence Precautions for Flash - Power-On Sequence Precautions for Flash - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)
Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English
At power-on, the FPGA automatically starts its configuration procedure. When the FPGA is in a master configuration mode, the configuration flash must be awake and ready to receive commands and/or clocks before the FPGA begins sending them. Special attention to the FPGA and flash power-on sequence or power-on ramps is essential. This is because different power rails can supply the FPGA and flash or because the FPGA and flash can respond at different times along the ramp of a shared power supply. The power-on sequence or power supply ramps can cause the FPGA to awaken or start before the flash, or vice versa. Some flash devices specify a minimum time period, which can be several milliseconds from power-on, during which the device must not be selected. For many systems with near-simultaneous power supply ramps, the default FPGA power-on reset time (TPOR) can sufficiently delay the start of the FPGA configuration procedure such that the flash becomes ready before the start of the FPGA configuration procedure.
Important: Master OSPI configuration mode with a bus width of x8 requires multi-function I/O configuration bank in addition to the VCCO_0 that is built into the power-on sequence requirement of the FPGA. Ensure the multi-function I/O configuration bank used is supplied at or before VCCO_0 to ensure proper configuration.

In general, the system design must consider the effect of the power sequence, the power ramps, FPGA power-on reset timing, and flash power-up timing on the timing relationship between the start of FPGA configuration and the readiness of the flash. Refer to the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) for FPGA power supply requirements and timing, and check the flash data sheet for the flash power-up timing requirements.

One of these system design approaches can ensure that the flash is ready to receive commands before the FPGA starts its configuration procedure:

  • Control the sequence of the power supplies such that the flash is certain to be powered and ready before the FPGA begins its configuration procedure.
  • Use the longer TPOR delay by connecting POR_OVERRIDE to GND.
  • Hold the FPGA INIT_B pin Low from power-up to delay the start of the FPGA configuration procedure. Release the INIT_B pin to High after the flash becomes ready.