Power-On Reset - Power-On Reset - UG860

To ensure proper power-on behavior, the guidelines in the respective family data sheet must be followed. For configuration, FPGAs require power on the V_{CCO_0}, V_CCAUX, V_CCBRAM , and V_CCINT pins (refer to Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) for more information). Power sequencing requirements are described in the data sheet. The power supplies should ramp monotonically within the power supply ramp time range specified in the data sheet. All supply voltages should be within the recommended operating ranges. Any dips in V_CCINT or V_CCAUX below their data retention voltages in the data sheet can result in loss of configuration data.

The FPGA automatically provides a delay between power-on and the beginning of configuration called the power-on reset (POR) delay. The POR delay count is short or long depending on POR_OVERRIDE. The T_POR delay starts from the time the last required supply rail is supplied to the FPGA at 95% of its nominal value and ends with the FPGA deasserting the INIT_B pin, sampling the Mode pins, and starting to toggle the CCLK if master mode is selected.