The Spartan UltraScale+ FPGAs configuration engine platform management controller (PMC) has different clock paths to support the new configuration modes and security features.
- The OSC_CORE_CLK is the internal oscillator clock that the device powers up from and that drives the Configuration Control Unit (CCU) clock CCU_IRO_CLK and the PMC dedicated configuration controller clock PMC_IRO_CLK.
- The eFUSE programming clock EFUSE_CLK source options are shown,
programmable logic (PL) FUSE_CLK or the External Master Configuration Clock
(
EMCCLK)pin. - The OSPI controller clock SPI_CLK source options to the OSPI controller clock are shown. The SPI_CLK drives the CCLK output to the Master SPI (SPI_24, SPI_32) and Master OSPI configuration modes.
The following figure provides the configuration and security feature clock sources for Spartan UltraScale+ FPGAs.
Figure 1. PMC Clocking Diagram
Figure Notes:
- The CCU_IRO_CLK frequency cannot be changed by the user during configuration. The BITSTREAM.POWER.CCU_CLK_FREQ option is for post-configuration advanced usage only.
- The PMC_IRO_CLK frequency cannot be changed by the user during configuration. The BITSTREAM.POWER.PMC_CLK_FREQ option is for post-configuration advanced usage only.
- For SPI/OSPI configuration modes.