Pin Descriptions - Pin Descriptions - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)

Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English

The following table defines the AXI32 pin connections.

Table 1. AXI32 Pin Descriptions
Pin Type Width Description
CLK input 1 PL AXI clock
ARVALID input 1 Read address valid
ARREADY output 1 Read address ready
ARID[7:0] input 8 Read address ID
ARADDR[27:0] input 28 Read address
ARLEN[3:0] input 4 Burst length
ARSIZE[2:0] input 3 Transfer size
ARBURST[1:0] input 2 Burst type
ARLOCK input 1 Lock type
ARCACHE[3:0] input 4 Memory type
ARPROT[2:0] input 3 Protection type
ARQOS[3:0] input 4 Quality of Service (QOS) identifier sent for each read transaction
AWVALID input 1 Write address valid
AWREADY output 1 Write address ready
AWID[7:0] input 8 Write address ID
AWADDR[27:0] input 28 Write address
AWLEN[3:0] input 4 Burst length
AWSIZE[2:0] input 3 Transfer size
AWBURST[1:0] input 2 Burst type
AWLOCK input 1 Lock type
AWCACHE[3:0] input 4 Memory type
AWPROT[2:0] input 3 Protection type
AWQOS[3:0] input 4 Quality of Service (QOS) identifier sent for each write transaction
WVALID input 1 Write valid
WREADY output 1 Write ready
WLAST input 1 Write last
WID[7:0] 1 input 8 Write ID tag (ignored)
WDATA[31:0] input 32 Write data
WSTRB[3:0] input 4 Write strobes
RVALID output 1 Read valid
RREADY input 1 Read ready
RLAST output 1 Read last
RID[7:0] output 8 Read ID tag
RRESP[1:0] output 2 Read response
RDATA[31:0] output 32 Read data
BVALID output 1 Write response valid
BREADY input 1 Response ready
BID[7:0] output 8 Response ID tag
BRESP[1:0] output 2 Write response
  1. The AXI32 primitive does not support write data interleaving. The WID[7:0] input pins are ignored and can be tied to zero.