Pin Descriptions - Pin Descriptions - UG860

Spartan UltraScale+ FPGAs Configuration User Guide (UG860)

Document_ID
UG860
Release_Date
2026-07-27
Revision
v1.3 English

The following table describes the USR_ACCESSE2 primitive pins.

Table 1. USR_ACCESSE2 Pin Descriptions
Pin Type Width Description
CFGCLK Output 1 Internal configuration control unit (CCU) clock
DATA[31:0] Output 32 Configuration Data reflecting the contents of the AXSS register
DATAVALID Output 1 Active-High Data Valid