The following table defines the BSCANE2 pin connections.
| Pin | Type | Width | Description |
|---|---|---|---|
| CAPTURE | Output | 1 | Asserted when TAP controller is in Capture-DR state. |
| DRCK | Output | 1 | Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or SHIFT are asserted. |
| RESET | Output | 1 | Asserted when TAP controller is in Test-Logic-Reset state. |
| RUNTEST | Output | 1 | Asserted when TAP controller is in Run-Test/Idle state. |
| SEL | Output | 1 | Asserted when the USER instruction (USER1 – USER4) that corresponds to the BSCANE2 instance's JTAG_CHAIN attribute (1–4) is loaded as the active instruction in the JTAG Instruction register. |
| SHIFT | Output | 1 | Asserted when TAP controller is in Shift-DR state. |
| TCK | Output | 1 | Test Clock. Primitive output from external TAP pin to FPGA internal logic. |
| TDI | Output | 1 | Test Data Input. Primitive output from external TAP pin to FPGA internal logic. |
| TDO | Input | 1 | Test Data Output. Primitive input from User internal scan register to a flip-flop that registers the primitive input on the falling edge of TCK. The output of the flip-flop is forwarded to the external TAP TDO pin. |
| TMS | Output | 1 | Test Mode Select. Primitive output from external TAP pin to FPGA internal logic. |
| UPDATE | Output | 1 | Asserted when TAP controller is in Update-DR state. Internal logic should update from the internal scan register on the rising edge of the UPDATE signal. |