The following figure describes the STARTUPE3 primitive pins. The
three-state controls default to 1 to disable the outputs,
KEYCLEARB defaults to a 1, and the other inputs default to
0.
| Pin | Type | Width | Description |
|---|---|---|---|
| CFGCLK | Output | 1 | Internal configuration control unit (CCU) clock output to the FPGA logic. |
| CFGMCLK | Output | 1 | Configuration internal oscillator clock output to the FPGA logic. CFGMCLK outputs a clock signal that is sourced from the FPGA internal oscillator. Refer to Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) for typical values and for the internal clock source core configuration tolerance. |
| DI(3:0) | Output | 4 | External D[03:00] configuration pin inputs that can be routed from STARTUPE3 to FPGA logic. |
| DO(3:0) | Input | 4 | FPGA logic signals that can be routed to STARTUPE3 to connect to the external D[03:00] configuration pins. |
| DTS(3:0) | Input | 4 | Three-state control of external D[03:00] output pins. |
| EOS | Output | 1 | Active-High signal indicating the end of start-up (EOS). EOS is an output into the FPGA logic. This output echoes the configuration logic EOS flag into the FPGA logic. EOS can be used as a reset signal. |
| FCSBO | Input | 1 | FPGA logic signal to external FCS_B configuration pin. FCSBO allows user control of FCS_B pin for Flash access. |
| FCSBTS | Input | 1 | Three-state control of external FCS_B output pin. |
| GSR | Input | 1 |
Not recommended – should be tied Low to disable. The GSR (Global Set/Reset) pin is an active-High input from the FPGA logic that asserts an asynchronous set/reset that can be used to re-initialize CLB flip-flops. The GSR signal spans the entire device and is released asynchronous to the user clocks. Due to the asynchronous release and skew across the device it is likely that flip-flops are not released in the same clock cycle, and it is possible to have a metastable event. Applications that use GSR should either stop all clocks before GSR and/or reconfigure the device after GSR. The same flip-flop initialization (set/reset) is performed safely during device configuration prior to startup. Note: GSR cannot be used for the signal
name.
|
| GTS | Input | 1 |
Global 3-state control. GTS is an active-High input from the FPGA logic. When this input is asserted High, all user I/Os except for configuration banks are put into a high-Z state. The GTS is automatically asserted during configuration and does not need to be asserted by the user. For most applications, this port should be tied Low. Note: GTS cannot be used for the signal
name.
|
| KEYCLEARB | Input | 1 | KEYCLEARB is used as a security use case tamper_fabric_b. When the tamper_fabric_b is set Low it will cause the tamper response to be executed. |
| PACK | Input | 1 | PROGRAM_B pin, JPROG or SYS_RST JTAG instruction, EAM SRST, or RST_PMC register request ACKnowledge. PACK is an input from the FPGA logic. This pin acknowledges the assertion of the external PROGRAM_B signal or internal instruction and allows the remainder of the PROGRAM_B state machine to continue resetting the FPGA. This pin is only enabled if the PROG_USR attribute is set. PACK can be tied Low for safe operations. |
| PREQ | Output | 1 | PROGRAM_B pulse, JPROG or SYS_RST JTAG instruction, EAM SRST, or RST_PMC register REQuest to the FPGA logic. PREQ is an output into the FPGA logic. This pin is the request from the PROGRAM_B state machine to reset the device. This allows the assertion of the PROGRAM_B request to be intercepted and gated until the design is in a state where the reset can be completed. For example, you might want to hold off device re-configuration to allow non-resettable data elements to be cleared. This pin is only enabled if the PROG_USR attribute is set. PREQ can be left open/floating for safe operation. |
| USRCCLKO | Input | 1 |
User CCLK input. USRCCLKO is an input from the FPGA logic. USERCCLKO drives a custom, FPGA-generated clock frequency onto the external FPGA CCLK pin. This is useful for post-configuration access of external flash devices. The delay from the internal USRCCLKO to the CCLK pin is defined as TUSRCCLKO in the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930). The first three clock cycles on USRCCLKO after EOS are used to switch the clock source and will not be output on the external CCLK pin. However, if the external master CCLK pin EMCCLK is used for configuration, it will continue to be seen on CCLK until the three clock cycles of USRCCLKO allow the transition to a new user clock. |
| USRCCLKTS | Input | 1 | The USR_CCLK_TS no longer tri-states the CCLK pin. |
| USRDONEO | Input | 1 | DONE pin output signal. USRDONEO is an input from the FPGA logic. This pin directly drives the external FPGA DONE pin. |
| USRDONETS | Input | 1 | DONE 3-state enable output to DONE pin. USRDONETS is an input from the FPGA logic. When this input is High, DONE is put into a high-Z state. Generally, this pin should be tied Low. Tying USRDONETS High inhibits the assertion of DONE. |