The following table describes the ICAPE3 primitive pins.
| Pin | Type | Width | Description |
|---|---|---|---|
| AVAIL | Output | 1 | ICAP available (for JTAG or MCAP interrupt). Allows FPGA logic to react properly. |
| CLK | Input | 1 | Clock input. When the ICAPE3 primitive is instantiated, the ICAPE3 CLK input is always used as the Readback CRC clock. |
| CSIB | Input | 1 | Active-Low ICAP input enable. |
| I[31:0] | Input | 32 | Configuration data input bus. |
| O[31:0] | Output | 32 | Configuration data output bus. If no data is being read, contains current status. |
| PRDONE | Output | 1 | Partial Reconfiguration complete. Default is High. Goes Low when FDRI packet is seen, and goes back High when DESYNC is seen and EOS is High. |
| PRERROR | Output | 1 | Partial Reconfiguration error. Default is Low. Goes High when partial configuration bitstream error is detected. Can be reset by loading RCRC command. |
| RDWRB | Input | 1 | Read (Active-High) or Write (Active-Low) Select input. |