POR_OVERRIDE - POR_OVERRIDE - UG860

The power-on reset override select (POR_OVERRIDE) pin must be set High or Low to determine the power-on delay before configuration begins. The POR_OVERRIDE is a logic input pin referenced between V_CCINT and GND. When V_{CCO_0}, V_CCAUX, V_CCBRAM, and V_CCINT power supplies are all ramped up to 95% of their normal value in a total time of <= 2 ms, the POR_OVERRIDE pin can be tied High at power-up (connected to the V_CCINT supply rail). The POR delay is shortened as specified in the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) (fast POR counter) with the POR_OVERRIDE pin tied High. When the POR_OVERRIDE pin is Low (connected to GND), the POR delay is longer (slow POR counter). Connect POR_OVERRIDE to GND unless the flash will always be ready as soon as the FPGA is powered up (see Power-On Sequence Precautions for Flash).

The device always waits for the V_CCINT power-on threshold to be met before determining the POR_OVERRIDE value, eliminating the possibility of false High readings. V_CCINT is recommended to ramp first.