Overview - Overview - UG860

This chapter provides a brief overview of the boot and configuration methods, updated configuration modes, and additional configuration security features for the Spartan UltraScale+ FPGAs. An optimized platform management controller (PMC) for device configuration with enhanced security is also included. The dedicated PMC configuration controller runs the fixed BootROM and platform loader and manager (PLM) code to initiate the device configuration process. Subsequent chapters provide detailed descriptions of each boot and configuration feature.

Like processors, AMD FPGAs are highly flexible user programmable logic devices. FPGAs can be reprogrammed in-system an unlimited number of times. The process of programming or loading the defining data into the FPGA is called configuration. After programming, the PL configuration data is stored in highly robust CMOS configuration latches (CCLs). Although CCLs are reprogrammable like SRAM, CCLs are designed primarily for data integrity. Because the FPGA PL configuration data is stored in CCLs, the device must be reconfigured after it is power cycled.

Configuration is designed to be flexible to accommodate different application needs and, wherever possible, to leverage existing system resources to minimize system costs. FPGAs can configure themselves automatically from an external, nonvolatile memory device. Alternatively, FPGAs can be downloaded or programmed by an external device, such as a microprocessor, DSP processor, microcontroller, PC, or board tester. The configuration data path can be serial to minimize pin requirements, including configuration through the industry-standard IEEE 1149.1 JTAG boundary-scan interface. A parallel configuration data path provides maximum performance and access to industry-standard interfaces, ideal for external data sources like processors.

For Spartan UltraScale+ FPGAs, the programmable device image (PDI) file defines the application-specific FPGA functionality programmed into the device. The PDI file contains the boot header, the platform loader manager fixed firmware for configuration and security, and the programmable logic (PL) data. The PDI is loaded into the FPGA through special configuration pins. These configuration pins serve as the interface for different configuration modes with various bus widths. See the configuration chapters for details on the specific supported configuration modes listed:

• Master Modes
  • Master SPI (x1, x2, x4)
  • Master OSPI (x1, x8)
• Slave Modes
  • Slave Serial (x1)
  • Slave SelectMAP (x8, x16, x32)
  • JTAG boundary-scan (x1)

The terms master and slave refer to the direction of the configuration clock (CCLK):

• In master configuration modes, the FPGA drives CCLK from an internal oscillator. For more information, see the Master Modes section. Optionally, external master configuration clock (EMCCLK) can be selected with a software option for advanced use cases. For more information, see the External Master Configuration Clock section.
• In slave configuration modes, CCLK is an input to the FPGA driven by an external host. For more information, see the Slave Modes section.

The specific configuration mode is selected by setting the appropriate level on the mode input pins M[2:0]. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors (<1 kΩ), or tied directly to ground or V_{CCO_0}.

The FPGA can also control its own configuration through internal connections from the FPGA logic to the configuration logic. The device can be either fully reprogrammed with an alternative design selected, or partial reconfiguration. This allows specific regions of the FPGA to be reprogrammed with new functionality while applications continue to run in the remainder of the device.